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@@ -1,23 +1,57 @@ |
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# Waveforms |
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*.vpd |
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########## Waveforms ####################################### |
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# Value Change Dumping (VCD) - IEEE Standard |
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*.vcd |
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# VCDlus Dumping (VPD) - Synopsys proprietary format |
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*.vpd |
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# Extended VCD (EVCD) - Dump only port information |
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*.evcd |
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# Fast Signal DataBase (FSDB) |
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*.fsdb |
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# Binary files |
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########## Simulation executable file ###################### |
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# Default name of the simulation executable. A different |
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# name can be specified with this switch (the associated |
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# daidir database name is also taken from here) |
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# -o <path>/<filename> |
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simv |
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# Directories used for compilation |
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csrc/ |
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########## Intermediate files used for simulation ########## |
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# Generated for Verilog top configs |
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simv.daidir/ |
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# Generated for VHDL top configs |
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simv.db.dir/ |
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# Infrastructure necessary to co-simulate SystemC models |
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# with Verilog/VHDL models. An alternate directory may |
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# be specified with this switch: |
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# -Mdir=<directory_path> |
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csrc/ |
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# Log files |
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########### Log files ###################################### |
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# The switch below allows to specify the file that will be |
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# used to write all messages from simulation |
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# -l <filename> |
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*.log |
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# DVE, UCLI related files |
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DVEfiles/ |
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ucli* |
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*.key |
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# Coverage related files |
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########## Coverage-related files ########################## |
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# Generation of coverage result reports is done with urg |
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# and the database location is specified with this switch: |
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# urg -dir <coverage_directory>.vdb |
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simv.vdb/ |
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urgReport/ |
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########## DVE, UCLI related files ######################### |
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# DVE produces some logs that are created in this directory. |
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DVEfiles/ |
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ucli.key |
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########## C Language interface ############################ |
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# When the design is elaborated for DirectC, VCS will create |
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# a file in the current directory with declarations for |
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# C/C++ functions. |
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vc_hdrs.h |